Atrenta Releases Industry's First Predictive Implementation Solution, Bringing Unmatched Speed, Accuracy and Capacity to System-On-Chip DevelopmentSearch: EDACafeCompany NewsDownloadsJob SearchCompany DirectoryProduct by Company NameProduct by CategoryProduct by NameProduct by Description Home | EDA Weekly | Companies | Downloads | e-Catalog | IP | Interviews | Forums | News | Resources | Check Email | Submit Material | Universities | Books | Events | Advertise | PCBCafe| Subscription | techjobscafe | ItZnewz | EDACafe EDA Portal, EDA News, EDA Jobs, EDA Presentations, EDA Newsgroups, Electronic Design Automation. Atrenta Releases Industry's First Predictive Implementation Solution, Bringing Unmatched Speed, Accuracy and Capacity to System-On-Chip Development "1Team Implement" Improves RTL Prototyping, Design and Floorplanning of Complex SoCs SAN JOSE, Calif., April 4, 2005 - Atrenta® Inc., a leading provider of advanced electronic design automation (EDA) solutions to the global semiconductor industry, today announced the availability of 1Team™ Implement, a breakthrough design automation solution enabling electronics companies to plan, design and implement complex systems-on-chips (SoCs) with far greater speed, accuracy and capacity than was previously possible. 1Team Implement is the first member of Atrenta's new 1Team Family of Predictive Development solutions (see related announcement). 1Team Implement is the industry's first unified physical planning, design and implementation solution, from architectural planning to RTL (register transfer level) design to initial placement. It provides SoC architects, logic designers and implementation teams with rapid, interactive guidance on the detailed physical implications of their designs, including timing, chip area, congestion and power consumption. At the RTL level, 1Team Implement brings the benefits of physical synthesis to SoC architects and logic designers--without the learning curve, expense and time required by traditional physical synthesis. At the implementation level, 1Team Implement performs rapid initial floorplanning of high-complexity designs. It can automatically perform mixed-size placement of multimillion-instance designs with hundreds of hard macros. In customer evaluations, the preproduction release of 1Team Implement placed high-quality, routable multimillion-gate designs in hours, compared to days using other tools. Used in conjunction with existing back-end implementation tools, 1Team Implement delivers industry-best quality of results, performance (both gate capacity and run time) and correlation. "1Team Implement is a true strategic advantage in today's increasingly complex and competitive electronics markets," said Atrenta's chief technology officer, Bernard Murphy. "1Team Implement can literally save months of development and millions of dollars. Its unequalled speed and gate capacity and its ability to steer development down the optimal path from planning through implementation, are keys to surviving the huge technical and economic challenges that SoC developers confront." Three Groundbreaking Products 1Team Implement consists of three tightly-coupled products: 1Team Architect is used by SoC architects to quickly evaluate key design trade-offs such as timing, die area and power. Users can rapidly explore what-if scenarios and scope out optimal design goals for the entire SoC, which are then handed off to the RTL design team. 1Team Create is used by logic designers to visualize the physical implications (including congestion, chip area and timing) of their RTL microarchitectures. Designers can close RTL and close timing early, reducing late-stage changes. 1Team Construct is used by physical implementation teams to quickly validate that timing and area projections can be met and to rapidly generate high-quality initial floorplans. 1Team Implement is built on industry standards, including Open Access database and .lib, SDC, LEF, DEF, PDEF interfaces. Each of the three products offers important advances over earlier-generation tools. 1Team Architect is unique in providing SoC architects with rapid, accurate feedback on the key physical trade-offs of their block-level architectures, unlike the rough estimates provided by previous architectural-level solutions. 1Team Architect accommodates partial RTL (VHDL and/or Verilog), hard IP, soft IP, and chip specifications. Users can examine the impacts of architectural decisions on physical variables such as timing, hierarchy, die size, row utilization, I/O pad placement, metal routing layers, unimplemented block area and block placement. Users can then tune their architectures to achieve the right balance of characteristics. 1Team Architect not only helps set the right goals; it drives downstream design planning and implementation to ensure that these goals are met. It generates partitioned RTL and constraints for hand-off to the logic design team. As design details are worked out, first by logic designers and later by the physical implementation team, this information is back-annotated in 1Team Architect. This allows the SoC architect to verify that all work is consistent with the desired intents and make adjustments where necessary to produce a successful outcome. 1T Create provides logic designers with precision guidance on the physical implications of their RTL designs. This is made possible by unique physical synthesis technologies that perform silicon virtual prototyping and floorplanning of a design at the RTL level--transparently and at interactive speeds. Logic designers get immediate feedback on crucial physical impacts such as timing, without leaving their familiar RTL environment. For instance, they can cross-probe between the timing report and their RTL code, quickly locating areas in need of improvement, making necessary adjustments and re-checking timing incrementally. This is a major improvement over existing alternatives such as conventional, gate-level physical synthesis, which is difficult for RTL designers to use and is very time-consuming due to capacity and runtime limitations. With 1T Create, designers can accomplish in minutes or hours what would otherwise take days. 1Team Create also includes a customizable physical rule checker for SDC constraints, physical hierarchy, timing, area and congestion. A signoff-quality static timing analyzer produces results which tightly correlate with industry-standard, gate-level timing analysis tools. 1Team Construct is a major milestone among physical implementation solutions. It is the only commercial tool with the ability to perform automatic floorplanning of designs with large numbers of mixed-size macro blocks and standard cells, quickly generating high-quality, routable floorplans ready for place and route by existing back-end implementation tools. Mixed-size placement has emerged as a critical design problem as SoCs increase in complexity and combine larger numbers of different-sized blocks. 1Team Construct also provides unprecedented capacity: the ability to perform block placement of entire multimillion-gate designs without partitioning. It can take designs with multiple millions of placeable instances and hundreds of hard macros, and create a high-quality placement in a matter of hours for the entire chip. In addition, a customizable physical rule checking environment enables users to capture best practices and apply them to their designs. Part of a Comprehensive Family 1Team Implement is one in a complete family of 1Team solutions that enhance key stages of system design, from planning through implementation and from SoC hardware development to embedded software development. 1Team solutions are fully compatible with industry standard tools, flows and methodologies and can be easily integrated into any standard design environment. Atrenta's solutions deliver the Predictive Development advantage with no disruption of current methodologies and infrastructures, enabling customers to reap much greater return from their existing design automation investments. About Atrenta Atrenta Inc. is the leading provider of Predictive Development solutions for companies creating complex electronic systems and systems-on-chips (SoCs). Predictive Development is a new class of design automation solution that turns the costly and error-prone activity of system development into a more predictable, manageable and reliable process. Atrenta's 1Team Family of Predictive Development solutions enhances the entire system development cycle--from architectural planning to physical implementation, and from hardware to embedded software. Atrenta is headquartered in San Jose, Calif., with a research and development center in Noida, India. For further information, visit the Atrenta website at www.atrenta.com, email moreinfo@atrenta.com or call 408-453-3333. Editorial Contact Jane Evans-Ryan - MCA, 650.968.8900, jryan@mcapr.com Atrenta Headquarters Mona Singh - Marketing Communications Manager, Atrenta Inc., 408.467.4248, mona@atrenta.com Copyright 1994 - 2005, Internet Business Systems, Inc. 1-888-44-WEB-44 --- Contact us, or visit our other sites: AECCafe DCCCafe TechJobsCafe GISCafe MCADCafe NanoTechCafe PCBCafe Privacy Policy